Recently, there is a tendency toward higher voltage for capacity enlargement in an electric storage system and a battery for mobility use, exploiting a secondary battery. For securing a higher voltage, an arrangement of a tandem connection of a plurality of batteries is used. As a semiconductor device (IC: integrated circuit) monitoring a voltage of a battery cell, there are currently produced various sorts of battery monitor ICs, each of which is able to measure the voltage of a plurality of tandem-connected batteries and to monitor an individual battery cell. This sort of IC has a function in which a plurality of ICs can be stacked in series in series in correspondence with the number of the batteries connected in series (see Non-Patent Literature 1). It is noted that the IC stack function corresponds to a daisy chain connection function for sequentially forwarding, e.g., command/data to respective neighboring ICs.
FIG. 10 schematically illustrates an example of a battery stack monitor IC 10 for multi-cells according to a related technique (see Non-Patent Literature 1). The IC 10 is connected to a plurality of cells connected in series (in the example of FIG. 10, 12 cells, though not limited thereto). Other 12-cells may be connected to an upper side and/or a lower side of the 12 cells. In case other 12-cell ICs are connected to each of the upper and lower sides of the 12-cell IC, a voltage of 12 cells×3=36 cells can be measured on a per cell basis by three ICs that are stack connected. Referring to FIG. 10, a multiplexer (MUX) 11 in the IC 10 selects a terminal pair (a positive electrode and a negative electrode) of a cell and an analog-to-digital converter (ADC) 12 converts a voltage of the selected cell to a digital signal. A digital signal output from the ADC 12 is transferred to a microprocessor (micro-computer), not shown, via a data bus (DATA) under control by a register control circuit (REGISTER AND CONTROL) 13. Command/data transmitted via the data bus (DATA) from the IC of a preceding stage are sent via the register control circuit 13 to a next following stage. In the example of FIG. 10, a MOSFET (a metal oxide semiconductor field effect transistor) discharge switch 14 is provided between the positive node and the negative of each battery cell, though not limited thereto. In case the cell voltage is measured by command setting from the microprocessor, as an example, the discharge switch 14, connected between the electrodes of the cell in question, is turned off (discharge switches of the upper as well as the lower sides of the cell in question are also turned off).
During a time of forwarding command or data, a chip select input pin (CSB1) of the IC10 is set to an activated state (e.g., LOW voltage), under control by a microcomputer, not shown. During this forwarding period, the command or data is sent from one stage to a following stage in synchronization with a clock signal. It is noted that, in the example shown in FIG. 10, the IC 10 buffers the chip select signal received from a chip select input pin (CSB1), in an inside of the IC 10, so as to output the so buffered signal at a chip select output pin (CSB0). The IC 10 also buffers the clock signal received from a clock input pin (CK1), in an inside of the IC 10, so as to output the so buffered clock signal at a clock output pin (CK0), thereby actuating the next stage IC. A positive power supply (V+) of the IC 10 is connected to a highest positive potential of the stacked cells (the positive potential of the topmost one of the stacked 12 cells), while a negative power supply (V−) is connected to the lowest negative potential of the stacked cells (the negative potential of the bottommost one of the 12 cells). The positive power supply (V+) of the IC 10 is connected to the negative power supply (V−) of the next stage IC, while the negative power supply (V−) of the IO 10 is connected to the positive power supply (V+) of the previous stage IC. TOS is a top setting pin of the stack (for example, TOS of the top device (IC) is at a HIGH voltage and TOS of each of the remaining devices (ICs) in the stack is at a LOW voltage). It is noted that the IC 10 may differentially input/output data on the data bus (DATA), for example, so that it is possible to provide a daisy chain connection among a plurality of ICs operating at respective different power supply potentials.
In the stackable ICs, it is necessary to effect functionality setting of each of the ICs stacked in order to send data of such as cell voltage that the IC acquired to e.g., a microcomputer.
The functionality setting of the ICs in many cases is by a hardware using an IC peripheral circuit. More specifically, a functionality setting pin of the IC is pulled up to a power supply voltage (VDD) or pulled down to a ground (GND) potential.
FIG. 7 is a diagram illustrating an example of a related technique relevant to the functional setting for the IC. Referring to FIG. 7, a plurality of stackable IC 11 to IC 13 and a microcomputer 2 are mounted on a board (circuit board) 3. IC 11 to IC13 are of the same configuration and electrically connected in series. A microcomputer 2 is connected to the ICs 13 to 11 via signal lines 53, 52, 51, respectively. Though not limited thereto, each of the ICs 11 to 13 may also be a battery stack monitor analogous to that shown in FIG. 10. In case each of the ICs 11 to 13 is a battery stack monitor shown in FIG. 10, the signal lines 53, 52, and 51 may include signals, such as a clock, a ship select signal or data explained with reference to FIG. 10.
The IC 13 that is connected to the microcomputer 2, is a master IC, with the other IC 13 and IC 12 being slave ICs. In the IC 13, functioning as the master IC, a setting pin that sets the function of the IC 13 and a power supply voltage (VDD) are connected together by a circuit (wiring) 43. In the IC 13 and IC 12, functioning as slaves ICs, GND and the setting pins are connected together by circuits (wirings) 41 and 42, respectively. It is noted that, in case each of the IC 11 to IC 13 is a battery stack monitor IC of FIG. 10, VDD is a positive power supply voltage V+ (positive potential of a top cell of the stacked 12 cells), while GND is a negative power supply voltage V− (negative potential of the bottom cell of the stacked 12 cells).
In place of mounting a plurality of stackable ICs 11 to 13 on one and the same board 3, as illustrated in FIG. 7, a plurality of stackable ICs may, in an alternative configuration, be mounted one by one on a plurality of different boards and connected together. For example, in an example configuration of FIG. 8, the ICs 11 to 13 are mounted on a plurality of boards 31 to 33 and connections of setting pins of the ICs 11 to 13 are changed over by switches 61 to 63. Or, as illustrated in FIG. 9, the design of boards 3A, 3B and 3C are changed in correspondence with respective functions.
In FIG. 8, a switch SW1 between GND and the setting pin of the IC 13 is opened and a switch SW2 between VDD and the setting pin closed to set the setting pin at the VDD potential. In the IC 11 and IC 12, switches SW2 between VDD and the setting pins are opened and the switches SW1 between the setting pins and GND are closed to set the setting pin at the GND potential.
Patent Literature 1 discloses a configuration of a cell voltage measurement device in which a voltage of each of a plurality of cells stacked together may be measured accurately. In this configuration, a cell side terminal for measuring a voltage of each individual cell is provided at a connection member of each of the stacked cells, and each cell side terminal is connected to a terminal of a GND connection changeover switch within the cell voltage measurement device provided in association with the connection member.
Regarding connection of a plurality of boards, Patent Literature 2 discloses a configuration in which a plurality of board units each of which is mounted on a mother board provided with a common bus line taking charge of signal communication, and a connector is provided at a terminal end of a common bus line of each of the board units, with a bias board that connects connectors of two neighboring board units and a terminal resistor attached to the connector of one of the board units.    Patent Literature 1: JP Patent Kokai Publication No. JP2012-242357A    Patent Literature 2: JP Patent Kokai Publication No. JP-S62-202598A